Edveon Design Verification Trainee Jobs 2026 | Apply Online
Design Verification Trainee at Edveon – Jobs 2026
Edveon is hiring Design Verification Trainees in Siruseri, Chennai, for candidates with 0–1 years of experience. Prior VLSI or Design Verification experience is not required, while engineering fundamentals, aptitude and logical thinking are important.
The role provides structured training in Digital Design & Verification, SystemVerilog, UVM basics and Analog Basics. Selected candidates can gain practical Design Verification exposure through training delivered by EdvLearn and Edveon’s engineering team.
Quick Job Details
| Job Detail | Information |
|---|---|
| Company | Edveon |
| Job Role | Design Verification Trainee |
| Qualification | B.E./B.Tech in ECE, EEE, CSE, IT or AI & DS; M.E./M.Tech in VLSI, Embedded Systems or Power Electronics |
| Experience | 0–1 years |
| Eligible Batch | 2023, 2024, 2025 and 2026 passouts |
| Location | Siruseri, Chennai |
| Work Mode | Not specified |
| Job Type | Not specified |
| Salary | Monthly stipend during training; amount not specified |
Role Overview
The trainee role focuses on developing semiconductor Design Verification fundamentals through structured training and practical exposure. Candidates should have strong aptitude, digital electronics knowledge, programming fundamentals and an interest in VLSI technology.
Key Responsibilities
- Apply aptitude, logical reasoning and problem-solving skills to technical problems.
- Use knowledge of Digital Electronics and programming fundamentals.
- Understand and apply technical concepts logically.
- Develop interest and practical capability in VLSI and semiconductor technology.
- Take ownership, learn continuously and persist through technical problems.
Eligibility & Required Skills
- Engineering candidates only.
- B.E./B.Tech in ECE, EEE, CSE, IT or AI & DS, or M.E./M.Tech in VLSI, Embedded Systems or Power Electronics.
- 2023, 2024, 2025 and 2026 passouts only.
- Programming fundamentals in C, C++, Java or Python.
- Good understanding of Digital Electronics, analytical thinking and problem solving.
Salary & Career Information
Selected candidates receive a monthly stipend during structured training, but the stipend amount is not specified. The program provides practical exposure to Design Verification and training in SystemVerilog, UVM basics, Digital Design & Verification and Analog Basics.
Recommended Skills & Learning Resources
Candidates should revise programming fundamentals and digital concepts before the written test. Focus on C, C++, Java or Python fundamentals along with Digital Electronics.
Interview Preparation
Prepare for aptitude, logical reasoning, Digital Electronics and programming questions. The supplied selection process also includes a Technical Assessment & Interview after eligibility screening and the written test.
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How to Apply for Edveon Design Verification Trainee
- Review the eligibility requirements carefully.
- Apply through the official Edveon opportunity page.
- Complete the eligibility screening and written test as applicable.
- Proceed through the technical assessment and interview if shortlisted.
- Selected candidates undergo structured training followed by assessment and full-time employment for selected candidates.
Who can apply for the Edveon Design Verification Trainee role?
Engineering candidates from the specified B.E./B.Tech or M.E./M.Tech disciplines who graduated in 2023, 2024, 2025 or 2026 can apply.
What stipend is offered?
The opportunity includes a monthly stipend during structured training, but the amount is not specified.
Is prior VLSI experience required?
No. The job details state that prior VLSI or Design Verification experience is not required.
Review the technical requirements, strengthen aptitude and programming fundamentals, and explore relevant engineering opportunities while preparing for the selection process.